1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a lead-less semiconductor device having a mounting substrate for mounting a chip, wherein the mounting substrate comprises a ceramic base with a surface, which has electrodes with improved-shapes thereon.
2. Description of the Related Art
FIG. 1A is a plan view of a first main face of a mounting substrate, wherein a bipolar transistor chip is bonded by metal wire-bonding. FIG. 1B is a plan view of a second main face of the mounting substrate of FIG. 1A. FIG. 1C is a cross sectional elevation view of a semiconductor device having the substrate of FIGS. 1A and 1B, taken along an X1-X1xe2x80x2 line in FIG. 1A. FIG. 1D is a cross sectional elevation view of a semiconductor device having the substrate of FIGS. 1A and 1B, taken along a Y1-Y1xe2x80x2 line in FIG. 1A. FIG. 1E is a plan view of electrodes on the first main face of the mounting substrate of FIG. 1A. FIG. 1F is a plan view of electrodes on the second main face of the mounting substrate of FIG. 1B. FIG. 1G is a cross sectional elevation view of the electrodes on the first and second main faces of the substrate of FIGS. 1E and 1F, taken along an X2-X2xe2x80x2 line in FIG. 1E. FIG. 1H is a cross sectional elevation view of the electrodes on the first and second main faces of the substrate of FIGS. 1E and 1F, taken along a Y2-Y2xe2x80x2 line in FIG. 1E.
With reference to FIGS. 1A through 1H, a semiconductor device 900 has a mounting substrate 910 and a sealing resin 7. The mounting substrate 910 has a first main face which is adjacent to the sealing resin 7 and a second main face which is positioned opposite to the first main face. On the first main face, a chip mounting electrode 920 is provided for mounting a semiconductor chip 20, and also first and second pad electrodes 930 and 940. On the second main face, first, second and third terminal electrodes 924, 934 and 944 are provided for external connections. The first terminal electrode 924 is connected through first and second via holes 921 and 922 to the chip mounting electrode 920. The second terminal electrode 934 is connected through a third via hole 931 to the first pad electrode 934. The third terminal electrode 944 is connected through a fourth via hole 941 to the second pad electrode 944. The semiconductor chip 20 has a first electrode 21 connected through a first metal bonding wire 8-1 and a second electrode 22 connected through a second metal bonding wire 8-2.
Respective sizes in FIG. 1E are assumed as follows. c1=1 mm. c2=0.5 mm. c3=0.1 mm. c4=0.325 mm. d1=0.5 mm. d2=0.45 mm. d3=d4=d5=0.15 mm. An estimated capacitance between the chip mounting electrode 920 and the first pad electrode 930 is then Ccbpkgx=60 fF. The characteristics of the transistor chip 20 are assumed as follows. A base resistance: Rb=14 ohms. A current gain cut-off frequency fT=16 GHz. A collector-base capacitance: Ccbchip=150 fF. If an emitter of the transistor chip is grounded, a maxim power gain Gmax at a frequency of 2 GHz is given by Gmax=[1/{8 xcfx80Rb(Ccbchip+Ccbpkgx)}]xc3x97(f/fT)=17.3 dB.
Since no electrically conductive pattern is provided between the chip mounting electrode 920 and the first pad electrode 930, the estimated capacitance Ccbpkgx between the chip mounting electrode 920 and the first pad electrode 930 is large, resulting in a large feed-back capacitance between input and output terminals and a reduced gain of the transistor chip.
In the above circumstances, it had been required to develop a novel lead-less semiconductor device free from the above problem.
Accordingly, it is an object of the present invention to provide a novel lead-less semiconductor device having a mounting substrate made of a ceramic-based material free from the above problems.
It is a further object of the present invention to provide a novel lead-less semiconductor device having electrode patterns of improved shapes for obtaining a reduced feed-back capacitance between input and output terminals.
It is a still further object of the present invention to provide a novel lead-less semiconductor device having electrode patterns of improved shapes for ensuring high maximum gain and suppressing any interference between input and output terminals.
The present invention provides a semiconductor device comprising: an insulating substrate have a first main face which is sealed with a sealing material; at least a set of input and output electrode patterns provided on the first main face, and the input and output electrode patterns being separated from each other; at least a ground electrode pattern having a ground potential, and the ground electrode pattern being separated from the input and output electrode patterns; and at least an electrically conductive pattern extending over an inter-region between the input and output electrode patterns, and the electrically conductive pattern being separated from the input and output electrode patterns, and the electrically conductive pattern being electrically connected to the ground electrode pattern, so that the electrically conductive pattern has a ground potential.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.